1. Field of the Invention
The present invention relates to lithography of semiconductor wafers. More particularly, the present invention relates to lithography using two lithography exposure sources to form a pattern.
2. Description of the Related Art
Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits (ICs) in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with others such as doping, and heat treatments. Layering is an operation used to add thin layers of material (typically insulator, semi-conductor or conductor) to the surface of the semiconductor wafer. Patterning is an operation that is used to remove specific portions of the top layer or layers on the wafer surface. Patterning is usually accomplished through the use of photolithography (also known as photomasking) to transfer the semiconductor design to the wafer surface.
The push to maintain Moore's Law is producing smaller and smaller semiconductor circuits. To produce the smaller sized devices, the useful lifetime for equipment designed for particular device sizes is often extended by using resolution enhancement techniques (RETs) on the photomasks. This increases the resolution available from the equipment. For example, alternating phase shift mask techniques as well as other optical proximity correction techniques are applied to photomasks to enhance the printing of device features. But the mask cost to produce resolution enhancement techniques (RET's) is growing exponentially. For example, suitable phase shift masks costs nearly an order of magnitude more than a standard binary mask (i.e., a mask without resolution enhancement).
In specific, currently, standard binary masks may cost on the order of $12 k, but an alternating aperture phase shift mask (AAPSM) costs $100 k or more. Increased capital costs for photomasks employing resolution enhancement techniques will likely have disparate impacts on the semiconductor industries. The application specific integrated circuit (ASIC) and the system-on-chip (SoC) industries will likely be impacted the most since the majority of their customers use a mask set to process only a few lots whereas the memory and CPU industries will process hundreds or thousands of lots per mask set.
One approach to these problems is elimination of the mask from the lithography process by direct write e-beam approach. But direct write lithography is very slow. Conventional lithography can process up to 100 wafers/hour, but direct write lithography may take as long as a day to process one wafer. Thus, the cost of ownership for direct write lithography may be 1,000 times greater per wafer as compared to conventional lithography. Extended write times also create CD control and defect issues and are not practical at the current time.
Accordingly, it is desirable to provide a more effective method for performing high-resolution lithography which includes higher throughput rates and lower costs of ownership.